
/*------------------- include --------------------*/

/*---------------------------------------------*/



module tb_cbb_dpram; 

reg clk ; 

reg rst_n;          //复位信号


//生成时钟
parameter NCLK = 1000/25.0;  // 25MHz
initial begin
	clk=0;
	forever clk=#(NCLK/2) ~clk; 
end 

initial begin
    $dumpfile("wave.vcd");
    $dumpvars(0, tb_cbb_dpram);   //dumpvars(深度, 实例化模块1，实例化模块2，.....)
end


reg [7:0] waddr , raddr , din ;
reg we , re ;
cbb_dpram
#(
    .ADDR_WIDTH    ( 8   )  ,    // 地址位宽
    .DATA_WIDTH    ( 8   )  ,    // 数据位宽
	.DATA_DEPTH    ( 256 )  ,    // 数据数量
    .CLEAR_ON_INIT ( 1   )  ,    // 是否清零
    .ENABLE_BYPASS ( 1   )  ,    // 是否输出旁路掉寄存器
    .ENABLE_ASYNC  ( 1   )       // 1:异步
) 
u_cbb_dpram_sclk
(
    .clk      (clk) ,
    .rst      (~rst_n) ,
    .raddress (raddr) ,
    .waddress (waddr) ,
    .re       (re) ,
    .we       (we) ,
    .i_data   (din) ,
    .o_data   () 
);


initial begin
    $display(" -------- psm sim ----------");
    rst_n = 0;
    din = 0;
    we = 0 ; 
    re = 0 ;
    waddr = 0 ; 
    raddr = 0 ;
    repeat(2) @(posedge clk) ;
    rst_n = 1 ; 
    repeat(10) @(posedge clk) ;

    repeat(1) begin
        @(posedge clk) begin we <= 1 ; din <= 1; waddr <=0 ; re <= 0 ;  raddr <=0 ; end
        @(posedge clk) begin we <= 0 ; din <= 1; waddr <=0 ; re <= 1 ;  raddr <=0 ; end
    end 



    @(posedge clk) begin we <= 0 ; din <= 1; waddr <=0 ; re <= 0 ;  raddr <=0 ; end
    repeat(10) @(posedge clk) ;
    $display("done!");
	$dumpflush;
	$finish;
	$stop;	
end



endmodule